/* Includes ------------------------------------------------------------------*/
#include "gt32f030.h"
#include "gt32f030_rcc.h"
/** @addtogroup GT32F030_StdPeriph_Driver
  * @{
  */


void RCC_AHBPeriphClockCmd(unsigned int RCC_AHBPeriph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));//	IS_RCC_AHB_PERIPH
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    RCC->AHBCKEN |= RCC_AHBPeriph;
  }
  else
  {
    RCC->AHBCKEN &= ~RCC_AHBPeriph;
  }
}


void RCC_APBPeriphClockCmd(unsigned int RCC_APBPeriph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_APB_PERIPH(RCC_APBPeriph));  
  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)
  {
    RCC->APBCKEN |= RCC_APBPeriph;
  }
  else
  {
    RCC->APBCKEN &= ~RCC_APBPeriph;
  }
}

void RCC_PeriphResetCmd(unsigned int RCC_APBPeriph, FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_RCC_PERIPH_RESET(RCC_APBPeriph));
  assert_param(IS_FUNCTIONAL_STATE(NewState));

	RCC->REGLOCK  = 0x55aa6699;
  if (NewState != DISABLE)
  {
    RCC->PERIRST |= RCC_APBPeriph;
  }
  else
  {
    RCC->PERIRST &= ~RCC_APBPeriph;
  }
	RCC->REGLOCK  = 0;
}

void RCC_SystemClkSwitch(unsigned int RCC_SysClkSel)
{
  /* Check the parameters */
  assert_param(IS_RCC_SYSCLKSEL(RCC_SysClkSel));

	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKSEL = 0x5a690000+RCC_SysClkSel;
	RCC->REGLOCK = 0;
}




//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
void RCC_EnableHIRC(void)
{
  unsigned int tp=RCC->CLKCR&0x8700; //1000_0111_00000000
	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKCR  = 0x5a690000+(tp|5);
	RCC->REGLOCK = 0;
}


void RCC_DisableHIRC(void)
{
  unsigned int tp=RCC->CLKCR&0x8700; //1000_0111_00000000
	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKCR  = 0x5a690000+(tp|4);
	RCC->REGLOCK = 0;
}


void RCC_EnableLIRC(void)
{
  unsigned int tp=RCC->CLKCR&0x8700; //1000_0111_00000000
	if(RCC->CLKSR&0x1)  //Pll_rdy
		tp |= 8;
		
	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKCR  = 0x5a690000+(tp|5);
	  while((RCC->CLKSR&BIT12)==0){}
	RCC->REGLOCK = 0;
}


void RCC_DisableLIRC(void)
{
  unsigned int tp=RCC->CLKCR&0x8700; //1000_0111_00000000
	if(RCC->CLKSR&0x1)  //Pll_rdy
		tp |= 8;
	
	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKCR  = 0x5a690000+(tp|1);
	RCC->REGLOCK = 0;
}


void RCC_EnablePLL(unsigned int pll_cfg)
{
  unsigned int tp=RCC->CLKCR&0x8704; //1000_0111_00000100

  assert_param(IS_RCC_PLLCFG(pll_cfg));

	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKCR  = 0x5a690000+(tp|9)+(pll_cfg<<8);
		while((RCC->CLKSR&1)==0);          //pll_rdy
	RCC->REGLOCK = 0;
}


void RCC_DisablePLL(void)
{
  unsigned int tp=RCC->CLKCR&0x8704; //1000_0111_00000100
	RCC->REGLOCK = 0x55aa6699;
	RCC->CLKCR  = 0x5a690000+(tp|1);
	RCC->REGLOCK = 0;
}

void RCC_SetAHBPrescaler(unsigned int RCC_AHBPrescaler) {
  assert_param(IS_RCC_AHB_DIV(RCC_AHBPrescaler));

  RCC->AHBCKDIV = RCC_AHBPrescaler;
}

void RCC_SetAPBPrescaler(unsigned int RCC_APBPrescaler) {
  assert_param(IS_RCC_APB_DIV(RCC_APBPrescaler));

  RCC->APBCKDIV = RCC_APBPrescaler;
}

/**
  * @}
  */ 

/************************ (C) COPYRIGHT Giantec-semi *****END OF FILE****/
